• DocumentCode
    439743
  • Title

    A dual-rail PLA with 2-input logic cells

  • Author

    Yamaoka, H. ; Yoshida, H. ; Ikeda, M. ; Asada, K.

  • Author_Institution
    University of Tokyo, Tokyo, Japan
  • fYear
    2002
  • fDate
    24-26 Sept. 2002
  • Firstpage
    203
  • Lastpage
    206
  • Abstract
    This paper presents a new dual-rail PLA with 2-input logic cells. The 2-input logic cells composed of pass-transistors can realize any 2-input Boolean function and are embedded in a dual-rail PLA without degradation of circuit performance. By using the logic cells, some classes of logic function can be implemented in a smaller circuit area, so that a high-speed and low-power operation is also achieved. The area advantage over the conventional design has been demonstrated by using PLA benchmark circuits. The measured results show that the proposed PLA operates correctly.
  • Keywords
    Boolean functions; Circuit optimization; Decoding; Degradation; Logic circuits; Logic design; Logic functions; Programmable logic arrays; Sequential circuits; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European
  • Conference_Location
    Florence, Italy
  • Type

    conf

  • Filename
    1471501