A low voltage fully-integrated 0.18um CMOS power amplifier for 5GHz WLAN

This paper presents design and measurement results of power amplifier (PA) for wireless local area network (WLAN) at 5 GHz using standard commercial CMOS 0.18 um process. The two-stage amplifier is implemented with all components fully integrated on chip including output matching network. Test results show that the power amplifier can achieve power gain of 15.1 dB, 1 dB compression power output (P-1) of 15.4 dBm, third order output interception point (OIP3) of 25.0 dBm and maximum power added efficiency (PAE) of 27.1% with low voltage operation of 1.8 V at 5.2 GHz. The die size is 1.2×0.7 mm². Literature survey indicates that this is probably the first reported CMOS PA at 5 GHz implemented in 0.18 um process working with a 1.8 V power supply, and this is fully-integrated one with high linearity and good efficiency.