A CMOS 7-Gb/s power-efficient 4-PAM transmitter

A novel power-efficient architecture for a multi-level PAM transmitter is proposed. A data look ahead technique is used to pre-switch the current sources so that drive current is reduced when transmitting small voltage levels. Interestingly, this transmitting small voltage need for a pre-driver block which also saves transmitter power. Based on this architecture, a 4-PAM transmitter is designed in 0.18µm standard digital CMOS technology. The transmitter achieves 3.5GS/s (7Gb/s) and occupies 0.16mm². The output driver and the entire transmitter consumed only 11.25mW and 66mW, respectively.