Title :
Analog timing recovery for noise-predictive DFE
Author :
Keane, J.P. ; Le, M.Q. ; Hurst, P.J.
Author_Institution :
University of California, Davis, CA, USA
Abstract :
A timing recovery architecture and its CMOS implementation are described for a noise-predictive decision-feedback equalizer (NPDFE). The 0.5µm CMOS prototype includes timing recovery and the NPDFE and operates at 160Mbps. The timing recovery blocks dissipate 27mW from 3.3V, occupy 0.2 mm2, and achieve a rms jitter of 50 ps, which is 0.8% of a bit period.
Keywords :
Clocks; Equalizers; Finite impulse response filter; Frequency; Magnetic noise; Magnetic recording; Quantization; Steady-state; Timing; Transfer functions;
Conference_Titel :
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European
Conference_Location :
Florence, Italy
