A continuous-time sigma-delta modulator with reduced jitter sensitivity

This paper introduces the implementation of a continuous time ΣΔ modulator with reduced jitter sensitivity for the first time to our knowledge. A previously published low power, 1.5V modulator with 12 bit resolution has been redesigned concerning the feedback D/A converter to implement a feedback pulse similar to switched capacitor modulators. A reduction of the jitter sensitivity by more than a decade could be obtained with this approach. The technique presented here has the potential to overcome one of the most severe concerns when building continuous time ΣΔ modulators compared to discrete time implementations.