A 15mW 280MHz 80dB gain CMOS limiting/logarithmic amplifier with active cascode gain-enhancement

This paper presents a low-power 280MHz limiting/logarithmic amplifier implemented in 0.6µm digital CMOS technology. Employing the proposed active cascode technique, the cascaded gain cells achieve 410MHz wide bandwidth. With the aid of cascading gain stages, the logarithmic evaluation of the input strength is acquired. The local DC-reference replica of the magnitude detector prevents the successive compression logarithmic function from process and temperature variations. With feedback-type DC-offset cancellation and a 2nd-order banpass filtering, the amplifier provides 800mVppconstant magnitude output for 68dB dynamic range input signal. The limting/logarithmic amplifier exhibits 80dB gain and ±1dB RSSI error. It achieves -78dB-V sensitivity and consumes 15mW from a single 3V supply. The active area occupies 0.36mm².