Title :
Current mirror evaluation logic: A new circuit style for high fan-in dynamic gates
Author :
Cakici, T. ; Roy, K.
Author_Institution :
Purdue University, West Lafayette, IN, USA
Abstract :
We propose a Current Mirror Evaluation Logic (CMEL) and show (for 0.13µm technology) that this new logic achieves 28-to-47% (10-to-27%) delay reduction against high fan-in single/multi-stage domino (conditional keeper domino [1]) OR gates at an affordable power and area penalty. In addition, CMEL shows 54-to-95% (18-to- 45%) delay reduction against high fan-in single stage (multi-stage) domino AND gates. Consequently, the proposed logic achieves high performance and noise immunity for high fan-in dynamic AND and OR gates, respectively, compared to that of conventional domino and conditional keeper domino circuits.
Keywords :
CMOS technology; Circuit noise; Crosstalk; Degradation; Delay; Leakage current; Logic circuits; Mirrors; Parasitic capacitance; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European
Conference_Location :
Florence, Italy
