A 10-Gb/s clock recovery circuit with linear phase detector and coupled two-stage ring oscillator

This paper describes the design and fabrication of a 10-Gb/s clock recovery circuit. This clock recovery circuit utilizes a novel half-rate linear phase detector. The voltage-controlled oscillator within the system consists of two two-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45 degrees. This coupled two-stage ring can osciliate in the frequency range of 3-11GHz The proposed clock recovery system is fabricated in a CMOS 0.18µm technology. The circuit dissipates 120mW power from a 1.8V power supply. The RMS jitter of the recovered clock is 2ps. The effective size of the layout is 250µm × 300µm.