DocumentCode :
439797
Title :
A 100MHz, 8mW ROM-less quadrature direct digital frequency synthesizer
Author :
Emira, A. ; Mohieldin, A.N. ; Sanchez-Sinencio, E.
Author_Institution :
Texas A&M University, College Station, TX, USA
fYear :
2002
fDate :
24-26 Sept. 2002
Firstpage :
427
Lastpage :
430
Abstract :
A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using ROM lookup table to store the sine values. ROM elimination has resulted in significant power and area savings. The proposed DDFS has been implemented using 0.5µm CMOS process and occupies 1.4mm2area. It achieves an extremely low power consumption of only 8mW at 100MHz and operates from a single 2.7V supply. The SFDR is better than 58dBc at low synthesized frequencies and the frequency resolution is 1.5kHz.
Keywords :
CMOS process; Communication switching; Energy consumption; Frequency synthesizers; Phase locked loops; Piecewise linear approximation; Piecewise linear techniques; Read only memory; Table lookup; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European
Conference_Location :
Florence, Italy
Type :
conf
Filename :
1471556
Link To Document :
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