DocumentCode
439804
Title
A 1.8-V, 6-bit, 1.3-GHz CMOS flash ADC in 0.25 µm CMOS
Author
Uyttenhove, K. ; Steyaert, M.
Author_Institution
K.U. Leuven, Heverlee, Belgium
fYear
2002
fDate
24-26 Sept. 2002
Firstpage
455
Lastpage
458
Abstract
The design and optimization of a high-speed, low-voltage CMOS flash analog to digital converter (ADC) is presented. The optimization procedures used during the design give the needed specifications of the different building blocks. The used analog power supply is only 1.8V. The maximum sampling speed is 1.3GHz, SNDR@133kHz is 33,2dB. SNDR@500MHz is 32dB. The total power consumption of the converter at full speed is 600µW and the total active area is only 0.13 mm2. The ADC is implemented in a 0.25 µm pure digital CMOS technology.
Keywords
Capacitance; Circuits; Clocks; Density estimation robust algorithm; Design methodology; Energy consumption; Error correction; Inverters; Low voltage; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European
Conference_Location
Florence, Italy
Type
conf
Filename
1471563
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