A 1.8-V, 6-bit, 1.3-GHz CMOS flash ADC in 0.25 µm CMOS

The design and optimization of a high-speed, low-voltage CMOS flash analog to digital converter (ADC) is presented. The optimization procedures used during the design give the needed specifications of the different building blocks. The used analog power supply is only 1.8V. The maximum sampling speed is 1.3GHz, SNDR@133kHz is 33,2dB. SNDR@500MHz is 32dB. The total power consumption of the converter at full speed is 600µW and the total active area is only 0.13 mm². The ADC is implemented in a 0.25 µm pure digital CMOS technology.