A CMOS analog FIR filter with low phase distortion

The FIR function of the proposed filter is realized by integrating weighted signal currents in a given time window on a capacitor. The input signal voltage is weighted into multiple voltages according to the FIR requirement through a resistor ladder. A switching network sequentially connects the weighted voltages to a linear transconductor which converts the voltage to current and charges the capacitor. The resulting capacitor voltage becomes the filter output, periodically available between integration and reset. In such a FIR filter, the hardware cost is de-linked to the number of taps. The filter was implemented in a 0.35 µm CMOS process. The measured side-band attenuation reaches 60 dB while the group delay is smaller than 11 ns, with a power consumption of about 35 mW at 3.3 V.