Optimising broadband signal transfer across long on-chip interconnect

Cross-connect switches with large port count require broadband signal transfer across long on-chip interconnect. The analysis and design of a matrix core for a 20-input, 20-output 12.5 Gb/s per input cross-connect switch are discussed. First, the signal transfer across an unloaded line is studied. A detailed analysis is used to map measured and simulated line data onto a lumped element model. Both differential and common mode parameters are fitted. The matrix node design procedure is explained, resulting in a multi-stage emitter follower-amplifier circuit. The transmission lines for both rows and columns of a matrix are crossing. Signal transfer across loaded transmission line with crossings is analysed and measurement results are presented. Experiments are performed in a 0.25 µm SiGe technology with 5-layer metal. Feasibility is shown of a 20×20, 12.5Gb/s matrix in this technology.