A novel 1-Gbps clock and data recovery architecture using synchronous oscillator in CMOS VLSI technology

A new fully integrated clock and data recovery (CDR) topology based on a synchronous oscillator (SO) is presented in this paper. Implemented in CMOS VLSI 0.25 µm technology, the circuit is dedicated to 1 Gbps point-to-point networks. It presents very low jitter measurements : 9.8 and 11 ps rms for respectively PRBS7 and PRBS31 patterns. The circuit exhibits some major advantages versus classical CDR based on PLL and DLL : no external component needed, low consumption and low locking time.