• DocumentCode
    44
  • Title

    A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part II: Drain Current Model

  • Author

    Duarte, Juan Pablo ; Sung-Jin Choi ; Dong-Il Moon ; Jae-Hyuk Ahn ; Jee-Yeon Kim ; Sungho Kim ; Yang-Kyu Choi

  • Author_Institution
    Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
  • Volume
    60
  • Issue
    2
  • fYear
    2013
  • fDate
    Feb. 2013
  • Firstpage
    848
  • Lastpage
    855
  • Abstract
    A universal drain current model for multiple-gate field-effect transistors (FETs) (Mug-FETs) is proposed. In Part I, a universal charge model was derived using the arbitrary potential method. Using this charge model, Pao-Sah´s integral is analytically carried out by approximating its integrand. The model describes both the subthreshold inversion for undoped FETs and the effects of finite doping density in the channel. With an explicit and continuous expression, the proposed drain current model covers all regions of device operation: subthreshold, linear, and saturation. The accuracy from the proposed model is comparable with that from well-known previous models for double-gate (DG) and cylindrical gate-all-around (Cy-GAA) FETs with an undoped channel. In addition, the model shows good agreement with 2-D and 3-D numerical simulations for doped-channel multiple-gate structures such as single-gate, DG, triple-gate, rectangular gate-all-around, and Cy-GAA FETs. The proposed model is well suited to be a core model for Mug-FETs due to its good computational efficiency and high accuracy; hence, it is useful for compact modeling.
  • Keywords
    field effect transistors; numerical analysis; semiconductor device models; 2D numerical simulation; 3D numerical simulation; Cy-GAA FET; DG FET; Mug-FET; Pao-Sah integral; arbitrary potential method; compact modeling; cylindrical gate-all-around FET; doped-channel multiple-gate structures; double-gate FET; finite doping density; multiple-gate field-effect transistors; rectangular gate-all-around FET; single-gate FET; subthreshold inversion; triple-gate FET; undoped FET; universal charge model; universal core model; universal drain current model; Computational modeling; FETs; Logic gates; Mathematical model; Numerical models; Numerical simulation; Semiconductor process modeling; Compact modeling; FinFET; Pao–Sah´s integral; Poisson´s equation; cylindrical gate-all-around (Cy-GAA) field-effect transistor (FET); double-gate (DG) FET; multiple-gate FET (Mug-FET); rectangular gate-all-around (Re-GAA) FET; semiconductor device modeling; single-gate (SG) FET; triple-gate (TG) FET;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2012.2233863
  • Filename
    6403538