Currents and capacitances in narrow width MOSFET structures

The trend towards smaller MOSFETs has proceeded to the point where one-dimensional device models are inadequate for predicting current and capacitance. Most investigators have focused their attention on two-dimensional models to account for short-channel effects. This paper shows that three-dimensional effects should be taken into account for more representative current and capacitance models for less than five-micron-wide-devices. For the standard four mask metal-gate process, an etch step defines the gate area. This etching process leads to tapered gate walls whose angle can vary from 45 degrees for single layer insulators down to smaller angles for multilayer insulators such as the widely used PSG-SiO2sandwich. As a result, there is not an abrupt transition in threshold voltage; consequently, there exists a taper component of channel current which gradually vanishes along the taper. For nominal operating conditions, the magnitude of this current component can be significant. For device modelling purposes, the taper component has been accounted for by an increase in device width has been accounted for by an increase in device width using first orser equations. In addition, a model for increased gatew and overlap capacitances due to the taper has been developed. Device data has been compared with predictions from the "effective width" current model. Results indicate that as smaller geometry MOSFET\´s are fabricated the taper angle around the gate must be increased if improvements in circuit performance and power reduction expected from minimum horizontal dimensions are to be realized