A new self-aligned planar array cell for ultra high density EPROMs

A novel process technology for producing a true cross-point EPROM cell is described in this paper. Buried N+ diffusions self-aligned to the Floating gate Avalanche injection MOS (FAMOS) transistor are used for the bit lines. These diffusions are covered with a planarized low temperature CVD oxide which isolates them from a perpendicular set of poly word lines. The bit line contacts and LOCOS isolation that are necessary for the industry standard cell have been eliminated. With this technology a 4 µm²cell using 1 µm design rules and zero alignment tolerance is feasible. The concept has been tested and verified using a 13.5 µm²test cell.