DocumentCode :
440217
Title :
Electrical Characterization and Modelling of Ultra-thin (1.8-3.4 nm) Gate Oxides
Author :
De Salvo, B. ; Clerc, R. ; Masson, P. ; Ahouassa, Y.P. ; Ghibaudo, G.
Author_Institution :
LPCS / ENSERG, Grenoble, France
Volume :
1
fYear :
1999
fDate :
13-15 Sept. 1999
Firstpage :
168
Lastpage :
171
Keywords :
CMOS technology; Capacitance measurement; Capacitance-voltage characteristics; Degradation; Dielectrics; Electrons; Energy barrier; Particle measurements; Thickness measurement; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference, 1999. Proceeding of the 29th European
Conference_Location :
Leuven, Belgium
Print_ISBN :
2-86332-245-1
Type :
conf
Filename :
1505466
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=440217
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