DocumentCode :
44033
Title :
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis
Author :
Hatai, Indranil ; Chakrabarti, Indrajit ; Banerjee, Swapna
Author_Institution :
Electron. & Electr. Commun. Eng. Dept., Indian Inst. of Technol., Kharagpur, Kharagpur, India
Volume :
62
Issue :
4
fYear :
2015
fDate :
Apr-15
Firstpage :
1071
Lastpage :
1080
Abstract :
This paper proposes an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coefficients can dynamically change in real time. To design an efficient reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit binary common sub-expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally within each coefficient. This technique is capable of reducing the average probability of use or the switching activity of the multiplier block adders by 6.2% and 19.6% as compared to that of two existing 2-bit and 3-bit BCSE algorithms respectively. ASIC implementation results of FIR filters using this multiplier show that the proposed VHBCSE algorithm is also successful in reducing the average power consumption by 32% and 52% along with an improvement in the area power product (APP) by 25% and 66% compared to those of the 2-bit and 3-bit BCSE algorithms respectively. As regards the implementation of FIR filter, improvements of 13% and 28% in area delay product (ADP) and 76.1% and 77.8% in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over those of the earlier multiple constant multiplication (MCM) algorithms, viz. faithfully rounded truncated multiple constant multiplication/accumulation (MCMAT) and multi-root binary partition graph (MBPG) respectively. Efficiency shown by the results of comparing the FPGA and ASIC implementations of the reconfigurable FIR filter designed using VHBCSE algorithm based constant multiplier establishes the suitability of the proposed algorithm for efficient fixed point reconfigurable FIR filter synthesis.
Keywords :
FIR filters; adders; application specific integrated circuits; circuit switching; matrix algebra; power consumption; probability; ADP; ASIC; FPGA; MBPG; MCM algorithm; MCMAT; PDP; VHBCSE algorithm; application-specific integrated circuit; area delay product; area power product; average probability; coefficient matrix; constant multiplier architecture; field-programmable gate array; finite impulse response filter; multiple constant multiplication/accumulation; multiplier block adder; multiroot binary partition graph; power consumption; power delay product; reconfigurable FIR filter synthesis; switching activity; variable-bit BCSE algorithm; vertical-horizontal binary common subexpression elimination algorithm; Adders; Algorithm design and analysis; Complexity theory; Finite impulse response filters; Hardware; Heuristic algorithms; Signal processing algorithms; BCSE algorithm; MCM; SDR system; VLSI design; reconfigurable FIR filter;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2015.2388838
Filename :
7027873
Link To Document :
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