Acoustic coprocessor for hmm based embedded speech recognition systems

Author

Bapat, Ojas A. ; Fastow, Richard M. ; Olson, Joe

Author_Institution

Spansion Inc., Sunnyvale, CA, USA

Volume

59

Issue

3

fYear

2013

fDate

Aug-13

Firstpage

629

Lastpage

633

Abstract

This paper describes a hardware accelerator for calculating observation probabilities in Hidden Markov Model based embedded speech recognition systems. The architecture integrates an 8-way data-path with a high bandwidth NOR Flash array and calculates senone scores for all senones in the acoustic library. This improves system response time by a factor of 2 (compared to software solutions running on just the embedded CPU), while consuming only 210mW power. The reduced recognition latency enables use of larger acoustic models thereby reducing the recognition word error rate by 15.4%. The hardware supports scoring of some or all senones in the acoustic library and speaker adaptation using feature vector transforms¹.

Keywords

coprocessors; hidden Markov models; logic gates; speech recognition; transforms; 8-way data-path; HMM based embedded speech recognition systems; NOR flash array; acoustic coprocessor; acoustic library; embedded CPU; feature vector transforms; hardware accelerator; hidden Markov model; observation probabilities; recognition word error rate; reduced recognition latency; software solutions; speaker adaptation; Acoustics; Coprocessors; Hardware; Hidden Markov models; Speech; Speech recognition; Vectors; Acoustic Modeling; Hardware Accelerator; NOR Flash; Speech Recognition;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/TCE.2013.6626249

Filename

6626249