Title :
A high performance deblocking filter hardware for high efficiency video coding
Author :
Ozcan, Erdem ; Adibelli, Yusuf ; Hamzaoglu, Ilker
Author_Institution :
Fac. of Eng. & Natural Sci., Sabanci Univ., Istanbul, Turkey
Abstract :
The recently developed High Efficiency Video Coding (HEVC) international video compression standard uses adaptive deblocking filter for reducing blocking artifacts. Deblocking filters increase both subjective and objective quality. But, they have high computational complexity. Therefore, in this paper, the first HEVC deblocking filter hardware in the literature is proposed. Two parallel datapaths are used in the proposed hardware in order to increase its performance. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code is verified to work correctly on an FPGA board. The proposed HEVC deblocking filter hardware can code 30 full HD (1920x1080) video frames per second. Therefore, it can be used in consumer electronics products that require a real-time HEVC encoder or decoder.
Keywords :
adaptive filters; computational complexity; consumer electronics; field programmable gate arrays; hardware description languages; video codecs; video coding; FPGA board; HEVC deblocking filter hardware; Verilog HDL; Verilog RTL code; adaptive deblocking filter; blocking artifacts; computational complexity; consumer electronics; high efficiency video coding; high performance deblocking filter hardware; international video compression standard; parallel datapaths; real-time HEVC decoder; real-time HEVC encoder; video frames; Clocks; Encoding; Field programmable gate arrays; Filtering; Filtering algorithms; Hardware; Hardware design languages; Deblocking Filter; FPGA; HEVC; HardwareImplementation;
Journal_Title :
Consumer Electronics, IEEE Transactions on
DOI :
10.1109/TCE.2013.6626260
