Title :
Low leakage design of LUT-based FPGAs
Author :
Lodi, Andrea ; Ciccarelli, Luca ; Loparco, Domenico ; Canegallo, Roberto ; Guerrieri, Roberto
Author_Institution :
ARCES, Bologna Univ., Italy
Abstract :
Moving to the 90nm node and below, in FPGA architectures, where there´s a large number of inactive transistors, power consumption due to subthreshold current becomes more and more relevant compared with the switching one. In this paper we analyze the leakage current associated to look up tables, the basic elaboration units of LUT-based FPGAs, giving a characterization in terms of timing performance, inactive and active leakage power consumption. We propose a circuit implementation to reduce leakage, avoiding delay and silicon area increase. The adopted solutions are based on multi-threshold and self reverse biasing techniques. As results we reduce the inactive leakage power by 88%, the active one by 64%, having 5% delay degradation and a negligible silicon area increase.
Keywords :
field programmable gate arrays; leakage currents; logic design; table lookup; timing; FPGA architecture; active leakage power; circuit implementation; delay degradation; inactive leakage power; inactive transistors; leakage current; leakage reduction; look up tables; low leakage design; multi-threshold technique; power consumption; self reverse biasing; subthreshold current; timing performance; Circuits; Degradation; Delay; Energy consumption; Field programmable gate arrays; Leakage current; Performance analysis; Silicon; Subthreshold current; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
Print_ISBN :
0-7803-9205-1
DOI :
10.1109/ESSCIR.2005.1541582
