Title :
A regular modular architecture for pipelined binary tree multipliers based on a sog structure
Author :
Testoni, Nicola ; Cisterni, Marco ; Franchi, Eleonora
Keywords :
Adders; Binary trees; CMOS technology; Circuit simulation; Costs; Delay lines; Field programmable gate arrays; Integrated circuit technology; Pipelines; Throughput;
Conference_Titel :
Research in Microelectronics and Electronics, 2005 PhD
Print_ISBN :
0-7803-9345-7
DOI :
10.1109/RME.2005.1543005
