Title :
A digital-PLL-based true random number generator
Author :
Liu, Chengxin ; McNeill, John
Author_Institution :
Electr. & Comput. Eng. Dept., Worcester Polytech. Inst., MA, USA
Abstract :
A true random number generator (RNG) based on a digital phase-locked loop (PLL) has been designed and implemented in a 1.5μm CMOS process. It achieved an output data rate of 100 kbps from the sampling of two 30MHz ring oscillators, and successfully passed the NIST test suite SP800-22.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; integrated circuit design; random number generation; 1.5 micron; 100 kbit/s; 30 MHz; CMOS process; digital phase locked loop; ring oscillator; true random number generator; Delay effects; Frequency; Jitter; Noise measurement; Phase locked loops; Phase measurement; Phase noise; Random number generation; Ring oscillators; White noise;
Conference_Titel :
Research in Microelectronics and Electronics, 2005 PhD
Print_ISBN :
0-7803-9345-7
DOI :
10.1109/RME.2005.1543017
