Title :
Hierarchical FPGA clustering to improve routability
Author :
Marrakchi, Zied ; Mrabet, Hayder ; Mehrez, Habib
Author_Institution :
LIP6-ASIM Lab., Univ. Paris 6, France
Abstract :
In this paper we present a new clustering technique, based on the multilevel partitioning, for hierarchical FPGAs. The purpose of this technique is to reduce area and power by considering routability in early steps of the CAD flow. We show that this technique can reduce the needed tracks in the routing step by 15% compared with the other packing tools.
Keywords :
field programmable gate arrays; logic CAD; logic partitioning; CAD flow; field programmable gate arrays; hierarchical FPGA clustering; multilevel partitioning; Clustering algorithms; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Logic devices; Pins; Reconfigurable logic; Routing; Switches; Table lookup;
Conference_Titel :
Research in Microelectronics and Electronics, 2005 PhD
Print_ISBN :
0-7803-9345-7
DOI :
10.1109/RME.2005.1543029
