Title :
HALOTIS - high accurate logic timing simulator
Author :
Ruiz-de-Clavijo, P. ; Bellido, M.J. ; Juan, J.
Author_Institution :
Dpto. Tecnologia Electronica, Univ. de Sevilla, Spain
Abstract :
This paper present a novel logic-timing simulator that includes the degradation delay model (DDM) called HALOTIS. DDM obtains high accuracy in glitches treatment and it has been included in HALOTIS simulation engine. Also, it is possible to estimate switching activity using it, and the results show a high accuracy in simulations when these are compared to HSPICE.
Keywords :
circuit simulation; logic simulation; HALOTIS simulation engine; degradation delay model; high accurate logic timing simulator; switching activity estimation; Circuit simulation; Computational modeling; Degradation; Delay; Distributed decision making; Energy consumption; Engines; Logic; Semiconductor device modeling; Timing;
Conference_Titel :
Research in Microelectronics and Electronics, 2005 PhD
Print_ISBN :
0-7803-9345-7
DOI :
10.1109/RME.2005.1543043
