DocumentCode
443492
Title
FPGA implementation of 1 Gbps real-time 4×4 MIMO-MLD
Author
Koike, Toshiaki ; Seki, Yukinaga ; Murata, Hidekazu ; Yoshida, Susumu ; Araki, Kiyomichi
Author_Institution
Graduate Sch. of Inf., Kyoto Univ., Japan
Volume
2
fYear
2005
fDate
30 May-1 June 2005
Firstpage
1110
Abstract
We developed two types of practical maximum-likelihood detectors (MLD) for multiple-input multiple-output (MIMO) systems with 1 Gbps-order real-time processing speed, using an FPGA device. We introduce two simplified metrics for implementations; referred to as a Manhattan metric and a correlation metric. In using the Manhattan metric, the detector needs no multiplication operations, at the cost of slight performance degradation within 1 dB. By using the correlation metric, the MIMO-MLD can significantly reduce the complexity in both multiplications and additions without any performance degradation. This paper demonstrates the BER performance of these MLD prototypes through the use of an all-digital baseband 4×4 MIMO testbed integrated on the same FPGA chip.
Keywords
MIMO systems; error statistics; field programmable gate arrays; maximum likelihood estimation; 1 Gbit/s; FPGA implementation; Manhattan metric; correlation metric; maximum-likelihood detectors; multiple-input multiple-output; real-time 4×4 MIMO-MLD; Baseband; Bit error rate; Costs; Degradation; Detectors; Field programmable gate arrays; MIMO; Maximum likelihood detection; Prototypes; Real time systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Vehicular Technology Conference, 2005. VTC 2005-Spring. 2005 IEEE 61st
ISSN
1550-2252
Print_ISBN
0-7803-8887-9
Type
conf
DOI
10.1109/VETECS.2005.1543479
Filename
1543479
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