DocumentCode :
44369
Title :
A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13- 
CMOS
Author :
Yuxiang Zheng ; Jin Liu ; Payne, Roger ; Morgan, Mark ; Hoi Lee
Author_Institution :
Dept. of Electr. Eng., Univ. of Texas at Dallas, Richardson, TX, USA
Volume :
21
Issue :
12
fYear :
2013
fDate :
Dec. 2013
Firstpage :
2274
Lastpage :
2285
Abstract :
This paper presents a between-pair skew (BPS) compensator for parallel data communications. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a wide-bandwidth voltage controlled data delay line. A 5-Gb/s sub-bit BPS compensator in 0.13- μm CMOS occupies approximately 0.038- mm2 active die area and dissipates 22.5 mW.
Keywords :
CMOS integrated circuits; correlation methods; data communication; delay lines; phase detectors; BPS compensator; between-pair skew compensator; bit rate 5 Gbit/s; continuous-time correlations; data sequences; parallel data communications; power 22.5 mW; size 0.13 mum; time skew; wide-bandwidth voltage controlled data delay line; Bandwidth; Clocks; Delay; Detectors; Latches; Receivers; Transfer functions; Between-pair skew (BPS) compensator; data skew detection; wide-bandwidth delay element;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2012.2232319
Filename :
6450117
Link To Document :
