CMOS integration of solid phase epitaxy for sub-50nm devices

In this work, we report a study of the integration of NMOS and PMOS junctions with solid phase epitaxy (SPE). For the first time, considerably improved short channel effects are demonstrated with SPE for both NMOS and PMOS (-30% / -25% in DIBL at L_g=40nm for N and P devices respectively). However, a 12/15% (NMOS/PMOS) Ion degradation is observed at V_d=0.9V that is explained by a contact resistance issue. Solving this contact resistance problem enables to recover the performance of spike annealed devices within 5%. Gate capacitance measurements demonstrate no significant poly-depletion degradation. Finally no degradation is reported for the poly-edge linear junction leakage and bulk-to-drain leakage. These results demonstrate the potentiality of SPE at the 45nm node and below.