Incorporation of supply voltage and process variations in the power optimization for future transistors

In this work, we extend this methodology to include the impact of supply voltage and process parameter variations (gate length, L_g , body thickness, T_si). A variation-aware methodology yields a realistic comparison between different device technology options at the future nodes. In addition, it gives a more measured assessment of both the minimum power possible as well as the optimal voltage-scaling roadmap. We show the efficacy and the wide scope of this methodology by applying it to a myriad of transistor related applications