DocumentCode :
445369
Title :
Sub-10 nm gate length metal/high-k SOI MOSFETs with NiSi/sub 2/ [111]-facetted full silicide source/drain
Author :
Watanabe, Y. ; Migita, S. ; Mise, N. ; Nabatame, T. ; Satake, H. ; Toriumi, A.
Author_Institution :
MIRAI-ASET, Tsukuba
Volume :
1
fYear :
2005
fDate :
22-22 June 2005
Firstpage :
197
Lastpage :
198
Abstract :
Metal/high-k SOI MOSFETs with NiSi2/Si (111)-facetted FUSI S/D are promising for aggressively scaled devices down to sub-10 nm gate length. The facet junction technique that we have developed works more effectively as the gate length becomes smaller. This device concept can be applied to 3D structures such as FinFETs, and it can also relieve the scaling of SOI thickness
Keywords :
MOSFET; high-temperature electronics; silicon compounds; silicon-on-insulator; MOSFET; NiSi2-Si; full silicide source/drain; high-k SOI; sub-10 nm gate length metal; Annealing; High K dielectric materials; High-K gate dielectrics; Immune system; Ion implantation; MOSFETs; Schottky barriers; Silicides; Silicon; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Device Research Conference Digest, 2005. DRC '05. 63rd
Conference_Location :
Santa Barbara, CA
Print_ISBN :
0-7803-9040-7
Type :
conf
DOI :
10.1109/DRC.2005.1553118
Filename :
1553118
Link To Document :
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