Effect of tensile capping layer on 3-D stress profiles in FinFET channels

Author

Shin, Kyoungsub ; Lauderdale, Todd ; King, Tsu-Jae

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA

Volume

1

fYear

2005

fDate

22-22 June 2005

Firstpage

201

Lastpage

202

Abstract

Strained-silicon technologies have been widely investigated to enhance the performance of CMOS devices (Thompson, et. al., 2005). In particular, strain induced by the use of a stressed SiNx capping layer is advantageous because of its process simplicity and its extendibility from bulk-Si to silicon-on-insulator (SOI) MOSFETs (Komoda, 2004, Pidin, 2004). In this paper, the effect of a tensile capping layer on the stress profile in the channel of a FinFET is studied for different channel-surface crystalline orientations and different fin aspect ratios, using the Ansys5.7 simulator

Keywords

CMOS integrated circuits; MOSFET; silicon-on-insulator; 3D stress profiles; Ansys5.7 simulator; CMOS devices; FinFET channels; channel surface crystalline orientations; fin aspect ratios; silicon on insulator; strained silicon technologies; tensile capping layer; Capacitive sensors; Compressive stress; Crystallization; Electronic mail; FETs; FinFETs; MOSFETs; Mechanical engineering; Silicon on insulator technology; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference Digest, 2005. DRC '05. 63rd

Conference_Location

Santa Barbara, CA

Print_ISBN

0-7803-9040-7

Type

conf

DOI

10.1109/DRC.2005.1553120

Filename

1553120