A digital LSI architecture of elastic graph matching and its FPGA implementation

The elastic graph matching (EGM) is known as an excellent algorithm in applications of human face recognition. This paper proposes a digital LSI architecture for EGM and a face/object recognition system using its FPGA implementation. In the EGM, the matching evaluation point graph is distorted to find the best trade-off between better matching in the feature space and less distortion of the evaluation point graph. In the proposed architecture, cache memory stores calculation results at the evaluation points and those at their neighboring pixels to reduce the calculation amount. In the FPGA implementation with a system clock of 48 MHz, EGM between the input and one memorized image can be performed in about 1 ms.