Application of novel hierarchical approach to formal verification of digital ICs

Author

El-Licy, Fatma A. ; Abdel-Aty-Zohdy, Hoda S.

Author_Institution

Dept. of Inf. & Comput. Sci., Cairo Univ.

Volume

1

fYear

2003

fDate

30-30 Dec. 2003

Firstpage

182

Abstract

A hierarchical approach for the abstraction of digital VLSICs is presented. Circuit layout is hierarchically abstracted into logical constructs of binary tree structures, which may be manipulated to extract circuit functionality for the purpose of verifying design correctness. VLSIC design specification in the form of HDL is hierarchically decomposed to generate logical formulae for the given specification. By comparing the above, a verification report is obtained

Keywords

VLSI; digital integrated circuits; formal verification; hardware description languages; integrated circuit layout; logic design; tree data structures; VLSI; binary tree structures; circuit layout; digital integrated circuit; formal verification; hardware description language; hierarchical abstraction; Binary trees; Boolean functions; Combinational circuits; Data structures; Electrical capacitance tomography; Formal verification; Hardware design languages; Logic design; Production; Very large scale integration; Binary Tree application; Digital ICs; Formal Verification; Hierarchical Approach;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003 IEEE 46th Midwest Symposium on

Conference_Location

Cairo

ISSN

1548-3746

Print_ISBN

0-7803-8294-3

Type

conf

DOI

10.1109/MWSCAS.2003.1562248

Filename

1562248