DocumentCode
446697
Title
A dual-modulus prescaler using double-edge-triggered D-flip-flops
Author
Huang, Hong-Yi ; Ho, Sheng-Feng ; Su, Hsuan-Yi
Author_Institution
Dept. of Electron. Eng., Fu-Jen Catholic Univ., Taipei
Volume
1
fYear
2003
fDate
30-30 Dec. 2003
Firstpage
209
Abstract
This work describes a CMOS dual-modulus prescaler using double-edge-triggered (DET) D-flip-flops. This technique enables a frequency synthesizer to be divided by 64/64.5. Simulation results show that 35% reduction of power dissipation can be obtained. Using a 0.25mum process, a dual-modulus prescaler can operate at 1.8GHz while dissipating 5.525 mW power
Keywords
CMOS logic circuits; UHF integrated circuits; flip-flops; frequency synthesizers; prescalers; 0.25 micron; 1.8 GHz; 5.525 mW; CMOS dual-modulus prescaler; double-edge-triggered D-flip-flops; frequency synthesizer; CMOS technology; Clocks; Counting circuits; Flip-flops; Frequency conversion; Frequency synthesizers; Phase detection; Signal design; Timing; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Conference_Location
Cairo
ISSN
1548-3746
Print_ISBN
0-7803-8294-3
Type
conf
DOI
10.1109/MWSCAS.2003.1562255
Filename
1562255
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