Control path in a protocol processor

In this paper a dual processor architecture dedicated for offloading of protocol processing tasks in network terminals is presented. The architecture includes one general purpose microcontroller handling control intensive tasks, and one programmable protocol processor (the PPP) accelerating data intensive tasks. The PPP uses a number of accelerators for datapath operation. The main focus of this paper is on how implementation of the PPP control path can be configured for different types of terminals, e.g. servers, gateways or desktop PCs. Static timing analysis in implemented layouts indicates that this architecture enables programmable TCP/IP offloading for multigigabit networks, when implemented in a mature process technology (0.35 mum)