Control path in a protocol processor

Author

Nordqvist, Ulf ; Liu, Dake

Author_Institution

Comput. Eng. Group, Linkoping Univ.

Volume

1

fYear

2003

fDate

30-30 Dec. 2003

Firstpage

524

Abstract

In this paper a dual processor architecture dedicated for offloading of protocol processing tasks in network terminals is presented. The architecture includes one general purpose microcontroller handling control intensive tasks, and one programmable protocol processor (the PPP) accelerating data intensive tasks. The PPP uses a number of accelerators for datapath operation. The main focus of this paper is on how implementation of the PPP control path can be configured for different types of terminals, e.g. servers, gateways or desktop PCs. Static timing analysis in implemented layouts indicates that this architecture enables programmable TCP/IP offloading for multigigabit networks, when implemented in a mature process technology (0.35 mum)

Keywords

microcontrollers; protocols; 0.35 micron; PPP control path; dual processor architecture; general purpose microcontroller; network terminals; programmable protocol processor; protocol processing tasks; static timing analysis; Acceleration; Bandwidth; Buffer storage; Communication system control; Computer architecture; Computer networks; Costs; Hardware; Network interfaces; Protocols;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003 IEEE 46th Midwest Symposium on

Conference_Location

Cairo

ISSN

1548-3746

Print_ISBN

0-7803-8294-3

Type

conf

DOI

10.1109/MWSCAS.2003.1562333

Filename

1562333