A VLSI architecture for finite ridgelet transform

This paper presents a VLSI architecture for the finite ridgelet transform (FRIT). The proposed architecture has been partitioned into two stages. First stage computes the finite Radon transform (FRAT) coefficients and the second stage computes 1-D discrete wavelet transform (DWT) coefficients. The simulation result shows that the core speed of the proposed architecture is around 66 MHz and the improvement over direct filter based implementation is 42.97%. The prototype is designed as an IP-block for SOC integration. The proposed architecture is prototyped using Verilog HDL and synthesized by Xilinx ISE development tools. "xc2v3000" device of Virtex-II device family has been used in this synthesis.