Montgomery modular multiplier architectures and hardware implementations for an RSA cryptosystem

This paper describes and analyses the Montgomery multiplication algorithm and proposes two scalable, systolic architectures and hardware implementations based on this algorithm in order to be used for an RSA module. The conventional architecture uses the original version of Montgomery multiplication algorithm and the optimized architecture a modified version of the algorithm. The second architecture is considerably better than the first one. Both architectures follow carry-save redundant logic and in comparison with other known architecture give interesting results in term of clock frequency, multiplication time and chip covered area