Title :
A GA hardware engine for post-fabrication clock-timing adjustment
Author :
Kajitani, Isamu ; Murakawa, Masahiro ; Takahashi, Eisuke ; Higuchi, Tatsuro
Author_Institution :
MIRAI, National Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan
Abstract :
This paper describes the development of a GA (genetic algorithm) hardware engine for post-fabrication clock-timing adjustment, focusing on two modifications, as well as its implementation on an FPGA (field programmable gate array). The first modification is to optimize the GA operation, to realize an improvement in yield rates of 31% (maximum). The second modification is to pre-specify certain GA parameters. Simulation results show that it is possible to pre-specify these parameters without affecting performance, allowing for the easy use of this adjustment method within the LSI fabrication process.
Keywords :
circuit optimisation; clocks; field programmable gate arrays; genetic algorithms; large scale integration; timing; FPGA; GA hardware engine; LSI fabrication process; field programmable gate arrays; genetic algorithm hardware engine; post-fabrication clock-timing adjustment; Built-in self-test; Clocks; Costs; Engines; Fabrication; Field programmable gate arrays; Hardware; Large scale integration; Testing; Timing;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562443
