DocumentCode
447651
Title
Embedded processors optimization with hardware in the loop
Author
Ghali, K. ; Hammami, O.
Author_Institution
ENSTA, Paris, France
Volume
1
fYear
2004
fDate
4-7 May 2004
Firstpage
561
Abstract
The design of an embedded microprocessor for a given workload is a tremendous task by itself due to the numerous parameters involved and the ranges of their possible values. If power consumption and area are also to be considered then the problem is even more complicated and requires a suitable framework and methodology for exploring the vast multidimensional space for such a problem. In this paper we propose such a framework based on direct execution on FPGA boards.
Keywords
field programmable gate arrays; microcomputer applications; microprocessor chips; FPGA boards; embedded microprocessor; embedded processors optimization; hardware in the loop; multidimensional space; power consumption; Energy consumption; Field programmable gate arrays; Hardware; Intellectual property; Iron; Microprocessors; Multidimensional systems; Process design; Space exploration; System-on-a-chip; FPGA; embedded; processor;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Electronics, 2004 IEEE International Symposium on
Print_ISBN
0-7803-8304-4
Type
conf
DOI
10.1109/ISIE.2004.1571868
Filename
1571868
Link To Document