Title :
Cache Hierarchy Optimization
Author :
Yavits, Leonid ; Morad, Amir ; Ginosar, Ran
Author_Institution :
Dept. of Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel
fDate :
July-Dec. 29 2014
Abstract :
Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing the CMP cache hierarchy and optimally allocating area among hierarchy levels under such constrained resources is developed. The optimization framework is extended by incorporating the impact of data sharing on cache miss rate. An analytical model for cache access time as a function of cache size is proposed and verified using CACTI simulation.
Keywords :
cache storage; network-on-chip; optimisation; power consumption; CACTI simulation; CMP; NoC; cache hierarchy optimization; chip area; chip multiprocessors; data sharing; network on chip; off-chip memory bandwidth; power consumption; Analytical models; Bandwidth; Computational modeling; Integrated circuit modeling; Multiprocessing systems; Optimization; Resource management; Analytical Performance Models; Cache Hierarchy; Chip Multiprocessor; Resource Allocation Optimization; Resource Allocation Optimizations;
Journal_Title :
Computer Architecture Letters
DOI :
10.1109/L-CA.2013.18
