DocumentCode
448777
Title
Behavioural synthesis of an adaptive Viterbi decoder
Author
Wolinski, M.Z. ; Reeve, J.S.
fYear
2005
fDate
19-20 Sept. 2005
Abstract
The synthesis of a hardware implementation of a Viterbi decoder from a behavioural specification is discussed. This is applied to a parallelized version of a BCH decoder. A parameterizable high-level VHDL model of the parallel decoder has been developed. Scalability of the parallel decoder in hardware is demonstrated. An extension of this technique to an adaptive decoder is discussed.
Keywords
BCH codes; Viterbi decoding; adaptive decoding; digital signal processing chips; hardware description languages; parallel algorithms; BCH decoder; DSP hardware design; adaptive Viterbi decoder; parallel decoder; parameterizable high-level VHDL model;
fLanguage
English
Publisher
iet
Conference_Titel
DSPenabledRadio, 2005. The 2nd IEE/EURASIP Conference on (Ref. No. 2005/11086)
Conference_Location
IET
ISSN
0537-9989
Print_ISBN
0-86341-560-1
Type
conf
Filename
1575340
Link To Document