VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity

With the superior error correction capability, low-density parity-check (LDPC) codes have initiated wide scale interests in wireless communication and storage fields. In the past, various structures of single code-rate LDPC decoders have been reported. However, to cover a wide range of service requirements and diverse interference conditions in wireless applications, LDPC decoders that can operate at both high and low code rates are desirable. In this paper, a 9k code length multi-rate LDPC decoder architecture is presented and implemented on a Xilinx FPGA device. Using pin selection, three operating modes, namely, the irregular 1/2 code, the regular 5/8 code and the regular 7/8 code, are supported. Furthermore, to suppress the error floor level, a characterization on the conditions for short cycles in a LDPC code matrix expanded from a small base matrix is presented, and a cycle elimination algorithm is developed to detect and break such short cycles. The effectiveness of the cycle elimination algorithm has been verified by both simulation and hardware measurements, which show that the error floor is suppressed to a much lower level without incurring any performance penalty. The implemented decoder is tested in an experimental LDPC-OFDM system and achieves the superior measured performance of block error rate below 10^-7 at SNR 1.8 dB.