Peak to average power ratio reduction in multi-band transmitters; analysis, design and FPGA implementation

This paper addresses the problem of peak to average power ratio (PAPR) reduction in multi-band transmitters. Transmitter linearity requirements are addressed and trade-off analysis for design and optimization of the PAPR reduction algorithm within the context of the error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) quality metrics are studied. Our study also includes mapping of the signal processing algorithms onto Xilinx Virtex-4trade field programmable gate array (FPGA) technology and addresses the device resource utilization and efficient hardware implementation of the above PAPR reduction algorithms onto the above mentioned device. Statistical simulations and performance assessments of the proposed algorithms are presented