DocumentCode
450381
Title
Layout System for the Random Logic Portion of MOS LSI
Author
Shirakawa, Isao ; Okuda, Noboru ; Harada, Takashi ; Tanu, S. ; Ozaki, Hiroshi
Author_Institution
Osaka University, Osaka, Japan
fYear
1980
fDate
23-25 June 1980
Firstpage
92
Lastpage
99
Abstract
The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multi-phase clocking system, and occupies ordinarily a considerable part of chip area. In this paper, a layout system for this portion of an LSI is described, which is constructed on the basis of a set of optimization heuristics. Experimental results of the layout system are also shown so as to reveal that the random logic portion can be realized in much the same area as can be done by manual layout.
Keywords
Boolean functions; Clocks; Computer displays; Large scale integration; Logic arrays; Logic circuits; Logic design; Logic gates; Permission; Read only memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1980. 17th Conference on
Print_ISBN
0-89791-020-6
Type
conf
DOI
10.1109/DAC.1980.1585234
Filename
1585234
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