Title :
A Hierarchical Approach for Layout Versus Circuit Consistency Check
Author :
Chao, Shiu-Ping ; Huang, Yen-Son ; Yam, Lap Man
Author_Institution :
National Semiconductor Corp., Santa Clara, CA
Abstract :
This paper describes a CAD program which checks the circuit topology and the electrical parameters from the IC layout data against the user supplied circuit descriptions. Taking advantage of the hierarchical characteristics of the layout data, the program achieves an efficient analysis and does a clear presentation of the results.
Keywords :
Circuit topology; Complexity theory; Computational geometry; Computer errors; Costs; Integrated circuit layout; Microprocessors; Parameter extraction; Permission; Very large scale integration;
Conference_Titel :
Design Automation, 1980. 17th Conference on
Print_ISBN :
0-89791-020-6
DOI :
10.1109/DAC.1980.1585255
