Abstract :
A new form of symbolic layout for integrated circuits is coupled with a mask compaction procedure which removes excess space while guaranteeing that all design rules are met. Trade-offs between X and Y compaction are made based on critical path information. Two types of compaction are used to minimize mask area and computer run-time. Additional procedures reduce mask area by inserting jogs at strategic locations in the layout. A partitioned data base is used to store mask data in a hierarchical manner. The symbolic layout and mask compaction procedures require only 30 to 50 percent of the time traditionally needed to do equivalent hand layouts. The global guidance information is used to control local compaction (clustering), automatic jog insertion, and global compaction procedures. These procedures make extensive use of design rule tolerance tests in reducing the area of the "initial placement" mask layout. The symbolic input is a loose topological description of the layout made up of single-connection-per-side symbols (e.g., transistors, interlayer contacts, etc.) and multiple-connection-per-side symbols (e.g., predefined RAMs, ROMs, flip-flops, etc.). The output is a legal mask description and graphical displays.
