Title :
A Multiple Delay Simulator for MOS LSI Circuits
Author :
Nham, H.N. ; Bose, A.K.
Author_Institution :
Bell Laboratories, Murray Hill, NJ
Abstract :
This paper describes a multiple delay simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. Integer rise and fall delays are associated with each transition and these delays are computed automatically based on device characteristics and circuit capacitances. The simulator has been extensively used for the design verification of production LSI chips.
Keywords :
Analytical models; Circuit simulation; Computational modeling; Costs; Delay; Large scale integration; Logic devices; MOSFETs; Permission; Timing;
Conference_Titel :
Design Automation, 1980. 17th Conference on
Print_ISBN :
0-89791-020-6
DOI :
10.1109/DAC.1980.1585310
