DocumentCode :
450446
Title :
MIXS: A Mixed Level Simulator for Large Digital System Logic Verification
Author :
Sasaki, Tohru ; Yamada, Akihiko ; Kato, Shunichi ; Nakazawa, Terufumi ; Omita, K. ; Nomizu, Nobuyoshi
Author_Institution :
Nippon Electric Co., Ltd., Tokyo, JAPAN
fYear :
1980
fDate :
23-25 June 1980
Firstpage :
626
Lastpage :
633
Abstract :
A mixed level simulator, MIXS, is a logic verification tool which has multiple simulation capabilities. Main MIXS techniques are time wheel and selective trace algorithm for functional level simulation based on ´node´ model concept and the linkage function of functional models, described in different detail, with network information. The mixed level simulation for large digital systems can be achieved very efficiently by using the above techniques.
Keywords :
Circuit simulation; Computational modeling; Computer bugs; Couplings; Digital systems; High level languages; Logic; Permission; Software testing; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1980. 17th Conference on
Print_ISBN :
0-89791-020-6
Type :
conf
DOI :
10.1109/DAC.1980.1585312
Filename :
1585312
Link To Document :
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