DocumentCode :
450482
Title :
Abstract Routing of Logic Networks for Custom Module Generation
Author :
Healey, S.T. ; Kubitz, W.J.
Author_Institution :
Kuck and Associates, Savoy, IL 61874 and Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
fYear :
1987
fDate :
28-1 June 1987
Firstpage :
230
Lastpage :
236
Abstract :
This paper describes a switchbox-type router for custom VLSI module generation as performed by a module planner. A module is decomposed into abstract cells consisting of global routes and boolean functional specifications. Each abstract cell is given to a cell synthesizer which generates the circuit layout and through-the-cell routing. Abstract routing for a module planner is in some sense similar to switchbox routing to the degree that all of the routes are generated internally within a rectangular boundary (routes are coming from four sides). The principle difference with respect to standard switchbox routing is at the geometric level, where a cell synthesizer generates the routing conduction layers along with circuit devices for each abstract cell within this rectangular region. The aspects of this paper which are thought to be novel contributions are 1) a relative pin assignment algorithm for the abstract cells; 2) a global routing penalty function which not only considers previous routes, but also considers gate complexity within the cells; 3) an efficient optimization algorithm for minimizing the number of tracks running through the module.
Keywords :
Circuits; Computer science; Drives; Logic arrays; Permission; Routing; Shape control; Silicon; Synthesizers; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1987. 24th Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0781-5
Type :
conf
DOI :
10.1109/DAC.1987.203248
Filename :
1586232
Link To Document :
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