Array Optimization for VLSI Synthesis

We present in this paper an algorithm that solves a general array optimization problem. The algorithm can be used for compacting Gate Matrix layouts, SLA´s, Weinberger Arrays, and for multiple folding of PLA´s. Our approach is based on the technique of simulated annealing. A major contribution of this paper is the formulation of the solution space which facilitates an effective search for an optimal solution. Experimental results are very encouraging.